This invention relates to transistor amplifier circuits, and more particularly, to an amplifier circuit having a bias compensation circuit for achieving higher output power and linearity as input power increases.
A linear RF power amplifier is commonly biased in class AB operation so as to achieve higher power-added efficiency. Linearity and power-added efficiency are two contradictory requirements in a power amplifier. A tradeoff between the linearity and power-added efficiency is needed for given specifications for the power amplifier. It is usually done by achieving the highest power-added efficiency for a given linearity requirement. This requires good control of the quiescent current of the power amplifier. Prior art techniques that provided good control of the quiescent current of the amplifier transistor used a simple current-mirror circuit with current gain without a bypass capacitor (U.S. Pat. No. 5,548,248).
However, in a conventionally biased class AB amplifier, the average bias supply current increases as RF input power increases. This increased average current results in an increased voltage drop in the resistive part of the bias circuit. This in turn reduces the average voltage drop across the forward-biased PN junction of the power amplifying transistor, pushing the amplifier into class B and even class C operations. Therefore, the output power will be saturated as the input power further increases. To overcome this problem, a boosting circuitry is usually used to increase the bias of the power transistor, such as a bias boosting circuitry, a self-bias boost scheme or an adjustable self-bias boost scheme. These boosting schemes, however, are usually not simple and compact enough.
Therefore, the object of the present invention is to provide a power amplifier circuit with a novel-biasing scheme, which is simple but capable of providing higher power output as the input power increases, as well as of good control of quiescent current of the power transistor.
To achieve the above object, the amplifier circuit of the present invention comprises an amplifying transistor and a dc bias circuit. The dc bias circuit comprises a first transistor in a current mirror with the amplifying transistor, and a second transistor to provide the base currents to both the amplifying transistor and the first transistor. A dc bias power source is coupled to the base of the second transistor through a resistor and an inductor connected in series. In addition, a bypass capacitor is connected between the common node of the resistor and the inductor and the ground. With the capacitor, an effective impedance at the emitter of the second transistor at high frequencies is smaller than that without the capacitor. This effectively makes the voltage drop across the base-emitter junction of the amplifying transistor larger than that without the capacitor at the signal frequency and therefore compensates the voltage drop. Furthermore, by properly scaling the emitter area ratio between the amplifying transistor and the first transistor, and/or the ratio between a bias resistor and a corresponding resistor coupled with the mirroring first transistor, the quiescent current in the amplifying transistor can be made to be in direct proportion to that of the first transistor.
Preferably the bypassing capacitor is an off-chip capacitor to permit flexibility and adjustment.